Critical Part Placement
No two designers will layout the same parts in the same manner. And no single designer is likely to layout parts in the same manner twice.
But when it comes to ensuring signal integrity, some part placement is critical. Until you know a bit more about board design, I encourage you to follow this section to locate and route a few of your parts.
1. USB, ESD, and SAMD11
High-speed traces get priority in routing. The highest speed nets in our design are the differential pair nets that connect the USB Connector to the SAMD11 microcontroller.
USB Bus Path
The USB Connector will have to be placed at the board edge with the ESD Diode D501 immediately next to it. On the other side of the ESD diode is the SAMD11 microcontroller.
The pins used on the diode were selected to allow this specific layout.
Considerations for J501, D501, and U501
The land pads from the usb connector need to be set back from the board edge by at least 15 mils.
There needs to be enough space between the components so that the courtyards do not overlap.
Additional components need to be near J501 and U501
This image shows the courtyards and pads for J501, D501, U501 and support components C502, R504, and C501 in one possible arrangement.
Bypass Capacitor C501
Bypass capacitors need to be placed as close as physically possible to their parent IC. They are placed in circuits to help alleviate the effects of ground bounce and to keep power ripples localized to a specific part of a circuit board.
When a digital switch changes state on a silicon die, it either starts, stops, or reverses current around a conductive path. A potential difference is immediately established that tries to prevent a change in flux in that circuit loop. The potential difference is established between the silicon die and the Land pad on the circuit board. During switching of digital gates, a potential difference exists between the silicon die ground and the PCB ground, a potential difference exists between the silicon die power rail and the pcb power rail.
The equation that governs the potential difference is given by:
Where L is the inductance formed by the conductive loop, dI is the change in current, and dt is the switching speed of the transistor gate.
For a more thorough discussion, see the articles I wrote here (What is Inductance and How Does it Apply to Ground Bounce?, How to Reduce Ground Bounce)
Image from AllAboutCircuits.com article on Inductance and Ground Bounce, Part 1
You can minimize L by placing decoupling capacitors as physically close as possible to the integrated circuit they serve.
"Ground Reference Potential" is more of a theoretical idea than it is a practical possibility, especially when shared across multiple devices. R504 allows the usb shield and the digital ground to reach the same potential over a long period of time, but not instantaneously, creating a new, unplanned for ground loop. With the shield a high-impedance return path, USB DP and DM have to couple to each other and USB_BUS must use the digital ground as the preferred return path.
C502 helps to quiet any noise that might transmit down the line and confine it to the connector and connecting wire.
You should find a way to keep these components (C502, R504) as close to one another as possible. One possible layout pattern that also keeps C501 close to U501 is shown below.