Schematic Capture

Schematic Capture is the process of creating your schematic inside an EDA.

5. Net Classes

5.1. Impedance Control

Impedance is a combination of resistance, capacitance, and inductance.  If an electromagnetic signal encounters a change in impedance at any point as it travels from source to destination, part of the signal energy will reflect, creating noise and dissipating energy.   So changes in impedance should be avoided wherever possible.  PCB Designers usually give high-speed signals the highest priority of all of their nets -- meaning they get routed first, and other signal lines have to work around them.

In our project, we will run a relatively low-speed differential pair a few millimeters between chip and connector, so we don't really need to worry about high-speed design, but we'll still go through the process as if we truly had a high-speed signal to worry about.

That means you should create a separate net for the differential pair that connects the USB Connector to the SAMD11

The first step in any high-speed design happens right after your schematic is finalized and before you route the first trace.  Call your PCB manufacturer and tell them you need trace and space guidelines for a high-speed net

Many free online impedance calculators are not accurate enough to use.  PCB fabricators (including Royal Circuits) often provide simple stackups free as a value-added service.  The stackup engineers will ask several questions, such as what board thickness, copper weight, number of layers, and dielectrics you plan to use.  The engineer will then provide you with specific trace and space guidelines using materials that are cost-effective and readily available.  

This 4-layer foil-on-core stack was generated for one of Royal's customers.  Note the distance between layers 1-2, 2-3, and 3-4

The provided trace & space guidelines only work for the layers they are calculated on.  If you plan to change layers, you will likely have to change trace and space widths as well.  Additionally, when routing your traces, you should not do anything that will change the impedance of your traces such as running them across traces on adjacent layers or routing them too close to vias, since the impedance will change when the amount of copper on adjacent layers changes.

Note the trace (Design line) is increased due to etch-compensation (actual line) and the width and spacing vary based on layer

One other thing to note -- the distance between copper layers 1-2, and 3-4 is small -- which means the impedance is small compared to layers 2-3.  The best design practice would be to route power and signal return paths between closely spaced layers -- but we'll save that for a future course on signal integrity.