Before you layout a circuit, it's generally a good idea to understand what is happening in your schematic. And before you lay out a schematic, it's generally a good idea to understand what is happening in your block diagram.
"This book is a bit technical. If you are a beginner, it's okay that you don't understand everything that follows -- your first project will still be successful. Try to pick up as much as you can, and ask questions in the forums!"
3. Data Bus Overview
The Real-Time Clock, BNO055, and BME280 all communicate with the ATMega328 via I²C.
The Inter-Integrated Circuit (I2C or I²C) protocol uses two data lines: clock and data. The Serial Clock Line (SCL) transmits the timing information while the Serial DAta line (SDA) transmits the bits of data. Either the master or the slave can trigger the data line, but only the master controls the clock. This allows for half-duplex communication between master and slave.
This animation of an I2C transaction is courtesy AllAboutCircuits.com
"A major misconception perpetuated by textbooks is the use of ideal square-waves in all design examples. These square waves are easy for authors to draw, but do not force students to think about the real-world effects of noise and impedance on signal propagation. Real circuits never have perfectly square edges. Noise, changes in impedance, cross-talk, etc... all keep the "square-waves" drawn in textbooks from ever appearing "square" in an actual circuit."
One of the advantages of the I²C protocol is that it is a multi-master, multi-slave protocol. Several microcontrollers can be on a bus and read the same sensor data, provided they aren't both controlling the clock signal at the same time. Usually, I²C is used by a single microcontroller to communicate with several slaves, such as EEPROM, sensors, displays, etc...
Many of the devices on the I²C bus have 7-bit addresses. With only <128 possible addresses (2^7=128, but not all addresses are used), it's entirely possible to select two devices with identical addresses. Fortunately, most manufacturers provide a workaround by adding an address (ADDR) or multipurpose (MP) pin to their design that allows designers to change the address by changing the logic level of a pin.
A second disadvantage is that high bus capacitance negatively impacts the maximum data rate. The I²C bus is meant for relatively slow, short-distance communication on a single board. While it can sometimes tolerate transmission via discrete wire connections to other boards, it is not designed for that purpose, especially at high speeds.
I²C Engineering Considerations
I²C master devices will pull the logic-signal directly to ground potential, and allow the pull-up resistors to bring the logic levels to Vcc potential. The logic-high to logic-low transition is fast and looks quite a bit like a square-waveform on an oscilloscope. But the logic-low to logic-high transition is mediated by the bus capacitance and the selection of pull-up resistors.
In the case of the I²C example, the RC-constant of the logic-high transition is the limiting factor in bus-speed. The resistance is provided largely by two pull-up resistors as well as a minor amount of trace resistance. The capacitance is the sum of trace capacitance, pin capacitance, and any other stray capacitance along the signal path. The I2C specification limits the maximum capacitance to 400 pF for standard (100 kHz) and fast mode (400 kHz), and 500 pF for fast mode plus (1 MHz). 400 pF is not a lot of capacitance. An individual I/O pin might have a capacitance of 2-10 pF, and a 6 mil trace increases capacitance by a little less than 2 pF/inch in FR-4 material above a ground plane.
Binary logic has two states: high and low. The logic high state of an integrated circuit might be any potential difference between 70% and 100% of Vcc, and the logic low state is often any potential difference between 0 and 30% of Vcc. In between 30% and 70% the logic is undefined. (These aren't the only logic thresholds, but are a good starting point for explanation sake.)
This is a slightly more realistic I2C clock signal. Image courtesy AllAboutCircuits.com
When the bus capacitance gets too high, the rising signal is unable to reach the logic-high state before the master device's logic-state changes and the signal falls back into a logic-low state.
This image shows the effects of too much capacitance and too much resistance which prevents the signal from ever reaching a logic-high state. Image courtesy AllAboutCircuits.com
To ensure that the signals reach the logic-high state in time, you should use a low-value pull-up resistor. But if the resistor value is too low, you risk running too much current through your microcontroller, and you will dissipate a great deal of energy every time you run an I²C transaction. Ideally, you will calculate the value of your pull up resistor based on the bus-capacitance and the I²C mode rise-time (standard, fast, or fast-mode plus).
The minimum resistor is much easier to calculate. The pins on your master and slave devices have maximum source/sink specifications listed in their datasheets. Find the lowest-value sink specification and use Ohm's law to calculate the minimum resistance.
To see more about how to calculate the I2C bus capacitance and resistance, see the article I wrote entitled I2C Design Mathematics: Capacitance and Resistance over at AllAboutCircuits.com