1. Overview

Schematic capture is the process of creating your design inside your EDA software.  This is the first step most people think of when it comes to design.  But as this course has shown, schematic capture is closers to step four or five than it is to step one.

Let's take a moment to back up. 

Several weeks ago, we began with a block diagram.  At the time we also presented a complete schematic and parts list.  When designing your own project, you won't have the schematic and parts list that early in the design process.  But you will have the block diagram that you drew and access to application notes/datasheets/etc...  that will hopefully provide sufficient information to allow you to build each of the blocks in your diagram.  In schematic capture, you will input all of the information you've collected (part numbers, component symbols, associated land patterns) into a single schematic document.

2. Flat vs. Hierarchical Layout

As a designer, you have multiple options for schematic organization.  Which one you choose will depend on EDA software, personal preference, and design complexity.

The overall organization of your design can either be flat or hierarchical.  

Option 1:  Flat Schematic Layout -- This design technique is meant for simple circuits.  The entire schematic is drawn on a single page, or split on multiple pages for ease of reading.  Sheet symbols all exist on the same level.  You can directly connect pins and parts on different pages.  If you've ever made a schematic, you've likely made a flat schematic.  For simple designs, you can use a flat organization, but if you make anything with more than two or three ICs, you will want to learn to use hierarchical layout techniques.

Option 2: Hierarchical Schematic Layout -- This design technique is meant for every moderate or high complexity circuit.  Every circuit block is replaced with a new symbol that shows only the inputs/outputs/connections to other circuit blocks.  Pull-up resistors, power connections, bypass capacitors, and every other bit of housekeeping is still shown on the schematic page for that block, but they are not shown on the parent page.  This allows someone reading the schematic to quickly develop a high-level overview of the function of the circuit without being bombarded by little details.  Then when it is time to inspect the details, they can open up the page that contains that element.

This image shows a single hierarchical element.  From Altium's "Creating Hierarchical Design"

In a hierarchical design, a parent-page shows the high-level overview, and child pages show increasing amounts of detail.  Child pages can only connect to a parent page, they cannot share connections with other child pages (there's usually a way to make it happen, it's just discouraged for most use-cases).

Image from Altium's "Creating Hierarchical Design" shows the relationship between the parent and the child pages.

There are other benefits of a hierarchical schematic.  

• Multiple designers can easily contribute their individual child schematic to a parent design.
• Circuit blocks (child pages) you create for one design can be easily transferred to another design.
• Child pages can often be nested several layers deep into the design

The top-level of our design shows 8 hierarchical blocks (the 9th, power, is not shown on this particular diagram).  Each block represents a child page.

The schematics for the Badge design are laid out in a hierarchical format out of necessity.  KiCad does not appear to have an option for a flat design.

When we started this course, we planned to use a flat-design, but KiCad seemed to require a hierarchical layout.  As the course has progressed, you've likely seen the schematic in both forms -- hierarchical in the online documentation I've created, and flat in Bob's original design files.  Future versions of this course will only show the hierarchical layout.

2.1. Begin A Hierarchical Layout

You can create this design in either a flat or a hierarchical layout unless you are using KiCad in which case you must use a hierarchical layout.

To begin a hierarchical layout, you will need to learn how to create parent sheets, child sheets, and hierarchical port connectors in your specific EDA software.  New schematic pages will need to be defined as hierarchical or changed to hierarchical after creation.

You will need one parent sheet (top-level) and 7-9 child sheets (secondary level), depending on how separated you'd like to keep everything.  

In the case of the schematic presented in this course, the child sheets are:

• MCU
• BNO055_IMU
• RTC
• BME_280
• SAMD11 USB Bootloader
• LCD
• SWITCHES
• LEDS | Buzzer
• Power

If you use larger schematic pages such as 11" x 17", or a multi-layer hierarchy you might reduce the number of sheets to the following:

• Microcontrollers
  • ATMega
  • SAMD11
• Sensors
  • BME280
  • BNO055
• Inputs Outputs
  • Switches
  • LEDs
  • Display
  • RTC
• Power

The names are arbitrary -- but make meaningful names.  Don't leave things labeled "Sheet 1", "Sheet 2", etc...

Once the sheet setup has been established, you can get to work capturing the schematic for that circuit block

3. Place Components

Last week you hopefully created a parts library for this design.  Now it's time to open it and place the parts. 

But before you do, I want to take a moment to jump forward in time. 

Once the schematic is complete, you will create a PCBLayout.  And many of the EDA programs used in this course initially explode parts onto the page.

A random part placement created by DipTrace

Some programs are better about part organization than others.  But usually, after the schematic is made, you've got to organize the parts -- put bypass capacitors near their respective ICs, placed programming headers near the parent IC, etc... 

Little things you do to organize the parts now will save you a great deal of time later.

RefDes Manipulation Option

Unique Reference Designators must be assigned to each part.  If you accidentally assign the same reference designator to two parts, you will get a DFA hold from your assembly shop, and they will require you to redesign your schematic to correct the error.  One option is to index the part numbers by 50, 100, etc... for each page of your design -- effectively assigning a prefix to the numerical descriptor.  That way, you can collect all the part numbers that have values 1xx, 2xx, 3xx, etc... and know they belong together on the PCB.  You can assign the numbers manually, or set a page index in your EDA software.  Look for something that refers to RefDes renumbering

All of the parts from one design block can be easily identified by part number

Other Software Options

Your specific EDA  software might have other tools to deal with the issue.  Altium uses Rooms, DipTrace offers RefDes Renumbering, etc...  You likely don't have to worry about the numbers until the schematic is fully drawn in your system.

4. Net Overview

Overview

After you place the parts in your design, and before you connect them with wires, you have hundreds of electrically disconnected pins.  As you start to connect them with wires, the pins begin to form networks.  The collection of wires that are electrically connected (short circuit) is referred to as a "net."  Your EDA software keeps track of the connections associated with each net.  Each pin belongs to only one net, and a single net can have an unlimited number of pins connected to it.

Inside the dotted rectangle the USB_D_P (Global) net is highlighted in blue and consists of 5 pin connections.  The left image shows the routed net on a PCB, the right image shows pins D501: I/0_1 (2), J501 (3): D+, USB_DP:1, USB_DP:1, and U501: PA25 (10) creating the net in the schematic diagram

Net Drawing

Connecting wires traditionally only run horizontally and vertically in a schematic diagram.  Wires that cross can either be connected or not.  If the wires that cross are connected at a junction point, a filled circular dot should appear in your diagram.

The six wires shown in this diagram cross at right angles.  Filled circular dots at t-shaped intersections (near green dots) indicate an electrical connection.  Missing dots near 4-way intersections indicate no connection.

These tie-points should be staggered at a 4-way intersection to improve readability -- forming t-shapes rather than plus-shapes.  Wires that are not connected that cross should do so at right angles without tie-points.

When multiple wires connect to the same net, they should be staggered instead of forming 4-way intersections

Wires that are connected need junction dots (shown in green), wires that are not connected should not have a junction dot (red).

Net Naming

You have to name your nets something meaningful.  Your EDA software will likely auto-name your nets programmatically.  Names such as net1, net2, net3, ...net137, are useless, but U2_1, U2_2, U2_3 might be useful.  You should name nets in a manner that makes sense to you and allows you to remember your design.

Special Nets

Power

Power nets are generally divided into two groups: Analog and Digital.  Analog power rails are expected to be free of ripple and noise, while digital power rails are expected to be noisy due to high-speed switching gates.  The are usually given the prefix or suffix A or D to differentiate the two in a mixed-signal design.  You might expect to see AVDD and DVDD in a mixed-signal single-rail design, or A5V0, D5V0, D3V3, etc... in a mixed-signal multiple rail design.  It is relatively common practice to see designers replace the decimal point with the letter V.  +3.0 and 3V0 are both fine, as long as they don't appear in the same design.  Use consistency in your naming conventions so that another designer can figure out your intentions. 

Serial Data Bus

Serial data buses are a prime spot for confusion.  That is because some data buses (SPI, I2C) require like-for-like connections while other data buses (UART) require a cross-over connection.  You can eliminate that problem by making all serial data buses like-for-like in the naming scheme.

SPI

Serial Peripheral Interface is easy.  MOSI connects to MOSI and MISO connects to MISO.  Net names of SPI_MISO and SPI_MOSI would work well for a single or multi-slave parallel setup.  Daisy chain configurations require a bit more thought.  If multiple MISO and MOSI lines exist, you might consider including part identifiers (SPI_MOSI_LCD_FONT, SPI_MISO_FONT_MEGA, etc...)  That way you are indicating the type of data bus, which data line you are using, where the wire starts and where it ends.  Whatever you decide, be consistent.

I2C

Inter-Integrated Circuit is another easy bus to name.  The parts are all connected in parallel, so naming the data bus and the data line should be sufficient to remind you of the wire function at a later date, I2C_SDA, and I2C_SCL, etc.   Try to resist the urge to label it I²C since the net names are usually printed in a small-sized font, and superscripts would be difficult to read.

UART

The UART data bus is where most mistakes happen.  A cross-over must occur between the receiver of one circuit and the transmitter of the next.  But you can reduce the chance of error by including the source and destination in the net name.  UART_MEGA_TX_SAM_RX and UART_MEGA_RX_SAM_TX.  These net names show the data-bus, where the wire starts and where the wire stops.  As long as the UART_MEGA_TX_SAM_RX wire starts at the MEGA UART Transmit pin and ends at the SAM UART Receive pin, the crossover has happened.

5. Net Classes

Some nets in a printed circuitboard design can have specific layout requirements that you can determine during schematic design.  Power nets might need to be of a minimum width to keep from overheating, impedance-controlled nets will need specific space and trace width, and high voltage nets must be kept a certain distance from other nets to prevent surface creepage or dielectric breakdown.

And where there is one net with specific design requirements, there are usually many more.  Rather than keep track of each net individually, engineers assign a group of nets to a class, and create design rules for the class.  Then, if they need to make a small design tweak later on, they can adjust all nets in a specific class at the same time.

While nothing in our current design really requires us to create special net-classes, we will go through the exercise so you'll know what to look out for in your next project.

5.1. Impedance Control

Impedance is a combination of resistance, capacitance, and inductance.  If an electromagnetic signal encounters a change in impedance at any point as it travels from source to destination, part of the signal energy will reflect, creating noise and dissipating energy.   So changes in impedance should be avoided wherever possible.  PCB Designers usually give high-speed signals the highest priority of all of their nets -- meaning they get routed first, and other signal lines have to work around them.

In our project, we will run a relatively low-speed differential pair a few millimeters between chip and connector, so we don't really need to worry about high-speed design, but we'll still go through the process as if we truly had a high-speed signal to worry about.

That means you should create a separate net for the differential pair that connects the USB Connector to the SAMD11

The first step in any high-speed design happens right after your schematic is finalized and before you route the first trace.  Call your PCB manufacturer and tell them you need trace and space guidelines for a high-speed net. 

Many free online impedance calculators are not accurate enough to use.  PCB fabricators (including Royal Circuits) often provide simple stackups free as a value-added service.  The stackup engineers will ask several questions, such as what board thickness, copper weight, number of layers, and dielectrics you plan to use.  The engineer will then provide you with specific trace and space guidelines using materials that are cost-effective and readily available.  

This 4-layer foil-on-core stack was generated for one of Royal's customers.  Note the distance between layers 1-2, 2-3, and 3-4

The provided trace & space guidelines only work for the layers they are calculated on.  If you plan to change layers, you will likely have to change trace and space widths as well.  Additionally, when routing your traces, you should not do anything that will change the impedance of your traces such as running them across traces on adjacent layers or routing them too close to vias, since the impedance will change when the amount of copper on adjacent layers changes.

Note the trace (Design line) is increased due to etch-compensation (actual line) and the width and spacing vary based on layer

One other thing to note -- the distance between copper layers 1-2, and 3-4 is small -- which means the impedance is small compared to layers 2-3.  The best design practice would be to route power and signal return paths between closely spaced layers -- but we'll save that for a future course on signal integrity.

5.2. High Current Traces

"We don't need to worry about this in our design.  However, as a rule of thumb, you should consider high currents as anything over 500 milliamperes of current.  This is a tad over-conservative, and you might not need special consideration for even a 1-ampere trace, but high currents can create high-heat, which shortens the lifespan of your PCB and components, and it can create fire, so it deserves at least a little of your time and attention."

Printed circuit board traces generate heat when charges travel through them and traces dissipate heat through conduction, convection, and radiation.  If the current is constant, the heat sources and the heat sinks will reach equilibrium and the trace will remain at a constant temperature that is above the ambient environmental temperature.

Heat Sources

As charges move through a conductor, some of their electrical energy is converted into thermal energy -- you might remember hearing this referred to as Joule heating or Ohmic-heating.  The rate of energy conversion is given as P=I²R. 

The square of the current is proportional to the heat generated.  So for a given trace, a 1-ampere current generates four times as much heat as a 0.5-ampere current.  A 2-ampere trace generates sixteen times as much heat as a 0.5-ampere trace.  In short, if you aren't paying attention, you can design a board that catches fire with very little effort.  This is common for new designers intent on squeezing as many traces as possible into as small an area as possible.

Heat Sinks

Heat transfers via three methods: Conduction, Convection, and Radiation. 

Radiation

At the temperatures that most PCBs operate, the net radiation flux is not a significant source of heat transfer -- the radiation energy emitted is only marginally greater than the radiation energy absorbed.  That leaves conduction and convection as the predominant sources of heat transfer in a printed circuit board.

Conduction

Conduction requires direct contact between materials to transfer thermal energy.  And materials that make good electrical conductors tend to make good thermal conductors.  You've likely already realized touching a metal railing on a hot day is much less pleasant that touching a wooden railing -- the metal can transfer energy at a greater rate than the wood.  The same is true in a PCB.  The metals/conductors (Copper, Silver, Tin, etc...) are able to conduct several orders of magnitude more heat energy than the dielectrics/insulators (FR-4, LPI Solder Mask, etc...), including the air that surrounds the board.  Heat energy can move through your board via conduction, but unless your PCB is attached to a metal frame or metal-fin heat-sinks, the heat energy generated inside your board cannot transfer off your board via conduction.

Convection

That leaves convection as the predominant source of cooling for most PCBs.  In convection, air molecules collide with a high-temperature part of a PCB and a small amount of thermal energy is transferred from the PCB to each of the air molecules.  That energy allows the molecules to spread out, decrease density, and get displaced upwards by cooler, less energetic molecules.  The PCB transfers thermal energy to the new molecules and the cycle endlessly repeats.

When natural convection isn't enough or isn't available, engineers can resort to heat-pipes, heat-fins, and forced-air to cool their boards (among other things).

If you have high-currents moving through your project, it is important to leave room for airflow inside your enclosure.

Designing for High Current Traces

You should know by the time you complete your schematic whether or not you have any high-current nets.  Datasheets indicate the maximum currents your parts might draw, and a detailed power budget can give you a decent idea of what current demands to expect from your power source.  You also need to know the operating environment of your board, the material properties of your dielectric, and if there are any heat-sensitive components near your trace.  If your trace gets too hot -- it can melt the dielectric material enough to damage it, and even moderate temperature excursions can force you to derate nearby passives or alter sensor readings.  So after you know your current requirements, decide what an allowable temperature increase in that part of the PCB might be.

With those details in hand, you can set to work defining the trace specifications.

Option 1: Estimate Using ICP-2152

"Most website trace-width calculators use IPC-2221, which is deprecated, do not use it.  IPC-2152 is based on empirically collected data, and offers less conservative results than IPC-2221"

If you have a plain PCB with no attached thermal features, such as pin/fin heat sinks, heat pipes, fans, etc..., convection is available to you, and you aren't in a harsh or high-altitude environment, you might consider the equations available in IPC-2152, and explored at length, by Dr. Douglas Brooks and Johannes Adam in the book PCB Trace and Via Currents and Temperatures: The Complete Analysis.  (The chapter Trace Currents and Temperatures Revisited, is available free from Dr. Brook's website Ultracad.com for free.) 

In the book, and the article, Drs. Brooks and Adam look at the relationship between current, temperature change, copper-weight, and trace-width.  You can use the equations provided to determine suitable trace widths for a variety of copper-weights.

Royal-Circuits took the equations for surface-traces and rearranged them for a variety of temperatures -- you can see the results in the appendix to the blog post: "Copper Trace and Space: Three Factors to Consider."  Here's an example graph from that post.  

In this graphic, the relationship between copper weight and trace width is shown for a surface trace that is allowed a 20° C temperature increase compared to its neighboring traces.  Internal traces or a PCB in a high-altitude environment would see a coefficient less than 215.3, which would shift all curves downward.

A 1-ounce external copper-weight is fairly common for a PCB.  Here the graph shows that 1-oz of copper that is ~7 mils wide can handle 1-A of current and only raises the trace by 20° C over ambient temperature.

Option 2: Simulate Using FEA or CFD Tools

Many of the popular 3D cad packages (Solidworks, Autodesk, etc...) come with advanced analysis and simulation tools.  Finite Element Analysis can model the conduction of heat around your PCB, while Computational Fluid Dynamics can handle convection.

If you'd like to explore the effect of adding a finned heat-sink to your design, an online simulator such as SimScale (free) might be of interest to you.

This model of convection currents around straight-fin heatsink is from SimScale.com

Option 3: Iterate using Thermocouples or Thermal Camera

There is no amount of simulation that can take into account every possible real-world variable.  If you are designing a motor-controller for an electric-vehicle, at some point you need to install your board inside your test vehicle and drive it out to the middle of Death-Valley National Park in the middle of a summer heatwave, point a thermal-imaging camera at it, and see where the hot points are.  Then you increase the copper surface area in those parts of the board.  Sometimes, it's not possible to put a thermal camera in a position to see a PCB in action, in those cases, engineers will install thermocouples at strategic points on a board, record it under operation, and make adjustments for the next revision.

Summary

Your PCB trace-width and copper thicknesses can be increased to handle high-currents.  Once you have determined an appropriate trace-width for your designed current, you can define a net-class for that current.  Then any nets in your design that must carry that current will be included in any future adjustments.  This makes changing copper weights a simple matter.

5.3. High Voltage Traces

"As a rule of thumb, high-voltage is a potential difference between any two nets over ~50 V.  You should not design high-voltage circuits until you have several board designs under your belt and understand the risks very well.  Even then, you should find an experienced power engineer to look over your layout."

When you are designing a circuit that you know is high-voltage or might be subject to strong nearby electric fields, special design considerations must be used to keep your project as well as nearby personnel and property safe.  And purposely designed low-voltage circuits can still sometimes need high-voltage protections at points where wires connect the board with the outside world.  

The two safety factors that power engineers often use are known as creepage and clearance.  Various standards bodies have generated standards based on the region the product will be sold/used and certified by an appropriate agency:  The European Committee for Electrotechnical Standardization CENELEC (EN), Underwriters Laboratory (UL), International Electrotechnical Commission (IEC), and Canadian Standards Association (CSA), German Electrotechnical Commission (DKE).

Image from Infineon Application Note AN 2012-10

Creepage

Creepage is the shortest straight-line distance between two conductors along the surface of a board (including the surfaces of enclosures, over parts, etc...).   Whenever a potential difference exists between two nets, the electric field can allow conductive paths to form over time.  The only way to prevent this (or significantly delay the onset) is to lower the electric field gradient to the point that conductors cannot be mobilized along that path.

Clearance

Clearance is the shortest three-dimensional distance between two conductors.  If a high-enough potential difference exists, charges can create an ionization path through air and discharge along the path.  While the electric field gradient needs to be much higher than the creepage gradient, it is still a very real possibility.  Fortunately, air and vacuum are self-healing dielectric mediums, unlike the insulation on wires, which once breeched, will remain weak for the duration of its service life.

6. File Backup and Versioning

Some EDA tools make backup and versioning easier than other EDA tools.  But it is very disappointing to lose all of your work due to a power failure or runtime error in your EDA software.  You should save your work frequently, and if possible, automatically.  Setup your software's auto-backup feature now, and you'll not be tempted to kick your computer later.  

Also, decide how you would like to keep track of revision and file-naming.  Unless you are working under the guidelines of your company, this will all be personal preference.

I have personally gotten into the habit of appending the date and sometimes time in year-month-day-hour-minute order to keep track of my files: examplefile_202005081018.txt is 05/08/2020 at 10:18 a.m. This keeps them arranged chronologically in my file directory and makes it easy to write a script to purge a directory of excess backups -- just sort alphabetically (usually the default option) and if there are more than 5 backups, delete all but the last 5.